Referring to FIG. 9, a flash memory cell consists of a single field effect transistor 2 having a floating gate FG which is used to set the state of the cell, and a control gate CG connected to a word line 8. As described later herein, application of programming voltages to the control gate, the source and the drain of a quiescent cell causes charge to be stored on the floating gate, whereby the cell assumes a condition referred to as a logical zero. The control gate, in cooperation with an erase voltage applied to the source via a line 10 can remove previously-stored charge on the floating gate, thus restoring the cell to the quiescent condition referred to as logical one. Flash memories have the ability to erase simultaneously all the cells of a portion of the memory, rather than to erase single cells. Application of read voltages to the cell enables determination of whether the cell is at the time storing a logical one or logical zero.
During the above-mentioned programming operation, which may be carded out one cell at a time, the source electrode--which is connected in common to source electrodes of other cells of the array by a source line 10 hereinafter referred to as the array ground line--is connected to a reference potential, such as ground. The control gate voltage of a cell to be programmed to logical zero is set at a relatively high voltage Vpp, such as plus 12 volts. The drains of pluralities of cells are connected together at respective bitlines and power applied to each bitline 6 to produce a predetermined voltage on the bitline, when a cell on that bit line is to be programmed.
Conveniently, the power may be applied to the bitline (and hence the drain electrode of a transistor to be programmed) by a source follower FET SF for connecting a supply voltage, e.g., the above-mentioned relatively high voltage Vpp to the bitline 6 via a load 32. The source follower has a gate driven by a stable voltage VST from a voltage regulator and a channel connected at one end to the bitline and at the other end to a supply source via the load 32. Thus, cell drain, or bitline, voltage during programming is determined at least in part by the output impedance of the source follower. This is because a source follower acts as a resistor whose value depends on the gate voltage applied thereto, --i.e. the level of current passed by the source follower depends on the gate voltage. When the source follower drain is at a constant voltage, the bitline voltage at the source of the source follower drops as current demand increases, and conversely rises as current demand falls.
During programming, as mentioned above, the control gate of a cell to be programmed receives a fixed relatively high voltage Vpp. The current drawn by the channel of the cell being programmed varies in the programming cycle between an initially high current demand and a later reduced current demand. Hence, application of a memory cell being programmed to the above-mentioned source follower gives rise to a voltage variation on the bitline as the current demand changes. When the memory cell channel current is high, the impedance of the source follower drops a relatively large voltage and therefore bitline voltage is relatively low, and as the current demand through the cell decreases, the bitline voltage rises. The relationship of bitline voltage to load current is referred to herein as the bitline loadline.
Since a source follower may be provided for each bitline, it is desirable that the source follower be physically small to minimize overall chip area demands. On the other hand, it is desirable to have a minimum source follower impedance when the source follower is turned on, i.e., during programming. As near as possible a constant cell voltage with variation of cell current is desired. This requirement tends towards use of a relatively large source follower. Consequently, any practical solution must be a compromise between the two requirements.
Two constraints on cell drain voltage are snap back and the time taken to achieve programming. These two effects are described later herein, and it suffices here to state that if the cell drain voltage exceeds an upper limit, snap back occurs and if cell drain voltage is below a lower limit, the time taken for programming will be unacceptably long.
As mentioned above, cell characteristics cause cell drain voltage to vary between initially low and later higher values during the course of programming. The cell drain voltage will also be influenced by other effects, such as temperature, supply voltage tolerances and process variations. The global maximum drain voltage resulting from all effects needs to be low enough to avoid snap back. The global minimum must be high enough to achieve sufficiently rapid programming to result in a satisfactory programming time.
It has been found that the level of drain voltage causing snap back and the drain voltage providing a maximum satisfactory programming time are dependent on the effective length of the cell. As the effective cell length increases, the snap back voltage, representing an upper limit to drain voltage, increases. Increase of effective cell length also causes the drain voltage for a particular duration of programming time to increase. Thus for a `short` cell, a relatively low first level of drain voltage causes snap back and a low second level of drain voltage provides reasonable programming time. For a `long` cell, a higher third level of drain voltage is allowable before snap back occurs and a higher fourth level of drain voltage provides the same reasonable programming time.
In one arrangement, the stable voltage VST applied to the source follower is selected to be a single value for an expected range of cell lengths. The voltage value selected must therefore set a loadline having a maximum drain voltage (corresponding to minimum cell channel current during programming) below the drain voltage causing snap back in a short cell and a minimum drain voltage (corresponding to maximum cell channel current during programming) above that voltage needed to give a selected programming time for a long cell. These two limits severely restrict the operation of the device.
Accordingly it is an object of the present invention to at least partially mitigate the above-mentioned disadvantage.